library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_register is
    -- define generic depth 
    generic(
        DEPTH : integer := 4
    );
    Port ( clk : in STD_LOGIC;
           clr : in std_logic;
           a : in STD_LOGIC;
           b : out STD_LOGIC);
end shift_register;
    
architecture slice of shift_register is
    -- define length of shift register from generic definition
    signal sr : std_logic_vector(DEPTH - 1 downto 0) := (others => '0'); 
begin
    process(clk)
    begin
        -- process on rising edge
        if rising_edge(clk) then
            if clr = '1' then
                sr <= (others => '0');
                b <= '0';     
            else 
                -- bitshift and concatenate input
                sr <= sr(sr'high -1 downto sr'low) & a;
                -- assign output
                b <= sr(sr'high);    
            end if;    
        end if;
    end process;

end slice;