library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity sr_TB is
--  Port ( );
end sr_TB;

architecture Behavioral of sr_TB is
    component shift_register is
        -- define generic depth 
        generic(
            DEPTH : integer := 10 -- notice that his varies from the entity declaration
        );
        Port ( clk : in STD_LOGIC;
            clr : in std_logic;
            a : in STD_LOGIC;
            b : out STD_LOGIC);
    end component;
    
    signal test_data : STD_LOGIC_VECTOR (0 TO 15) := b"1100110101011010"; -- some binary input data
    signal clk :STD_LOGIC := '0'; 
    signal clr :std_logic := '0';
    signal a: std_logic := '0' ;
    signal b: std_logic;
    
begin
    UUT: shift_register port map(clk => clk, clr => clr, a => a, b=> b);
    -- Define clock input
    clock_process: process
    begin
        clk <= '1';
        wait for 10 ns;
        clk <= '0';
        wait for 10 ns;
    end process;
    
    shift_data: process
    begin   
        wait for 100 ns;
        clr <= '1';
        wait for 20 ns;
        clr <= '0';
        wait for 20 ns;
        -- loop through sample data stream
        for i in 0 to 15 loop
            wait for 20ns; 
            a <= test_data(i);
        end loop; 
        wait for 100ns;
    end process;     
end Behavioral;