`timescale 1ns / 1ps

module PatternDetector (
	input clk,
	input reset,
	input x,
	output y);
	
	//initialize state register
	reg [1:0] state = 0; /* synthesis keep */
	//declare parameters to use as "states"
	parameter S0 = 0, S1 = 1, S2 = 2;
	//note we are not using real states, but rather using a parameter
	//to keep track of our firmware like a state
	
	//create process to handle state transition
	always @ (posedge clk)
	begin
		case(state)
			S0: begin
				y <= 0;
				if(x=1) begin
					state <= S1;
            end else begin
					state <= S0;
            end
			end
			
			S1: begin
				y <= 0;
				if(x=1) begin
					state <= S2;
            end else begin
					state <= S0;
            end
			end
			
			S2: begin
				y <= 1;
				if(x=1) begin
					state <= S1;
            end else begin
					state <= S0;
            end
			end
			
			default: state <= S0;
		endcase
	end
endmodule