library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm is
    Port ( clk : in STD_LOGIC;
           x : in STD_LOGIC;
           rst : STD_LOGIC;
           start : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is
    TYPE STATE_TYPE IS (s0, s1, s2, s3, s4);
    SIGNAL state : STATE_TYPE;
begin
    -- Define the progression of states
    PROCESS(clk, rst)
    BEGIN
        IF rst = '1' THEN
            state <= s0;
            start <= '0';
        ELSIF (clk'EVENT AND clk = '1') THEN
            CASE state IS
                WHEN s0=>
                    if x = '0' THEN

                    ELSE

                    END IF;
                WHEN s1=>
                    if x = '0' THEN

                    ELSE

                    END IF;                    
                WHEN s2=>
                    if x = '0' THEN

                    ELSE

                    END IF; 
                WHEN s3=>
                    if x = '0' THEN

                    ELSE

                    END IF; 
                WHEN s4=>
                    if x = '0' THEN

                    ELSE

                    END IF;                                
            END CASE;
        END IF; 
    END PROCESS;

end Behavioral;