Department of Electrical and Computer Engineering

ECED 4260 IC Design and Fabrication

Lab3 More Digital Design-Structural VHDL and Behavior VHDL

OBJECTIVES 

       Create a structural 2 bit x 2 bit multiplier using multiple instantiations and hierarchy.

       Create a sequential pattern detector using both behavioral and structural techniques, such that it is synthesizable with Quartus II software and ready for FPGA programming, and test the circuit.

Part I : Create a Structural 2 bit x 2 bit multiplier

In this part of the lab you are going to create a modular 1-bit multiplier, convert it to a 2-bit x 2-bit multiplier.

Lab help document can be downloaded here

For multiplier let's start from simple 1-bit x 1-bit. Assume we have individual multiplier bits "m" and "q", and we multiply them to get the product p. We have following truth table:

m	q	p
0	0	0
0	1	0
1	0	0
1	1	1

It is a AND function which serves as the core of the multiplication function. 

While a 1-bit multiplier is functional, it is severely limited in its ability to perform any useful multiplication. We need to add some additional logic beyond it to cascade the 1-bit cell. following are the observations:

			1	2	3
		x	2	3	4
0	0	0	4	9	2
0	0	3	6	9	0
0	2	4	6	0	0
0	3	8	7	8	2

1. Use above three decimal number multiplication, it can be shown that there is essentially no difference in the method of multiplication for a base-2 system than from a base-10 system.
2. Initial multiplier stages or those stages at the periphery of the multiplier do not require a partial product from a previous stage, since there is no previous partial product.
3. The initial portion of the partial production sums so not require a carry, since there is nothing added before them
4. Individual inputs for different stages of the multiplication are made available for an entire array of multiplier cells across one dimension.

With those observations and conditions , a fully cascadable 1-bit multiplier cell can be developed, which consists of:

1. Inputs bits "m" and "q" for multiplication.
2. partial production input bit "pp" that accepts partial products from previous stages.
3. output bit "p" that is the addition of the partial production "pp" and the product "m x q", and is the product result for the current stage and the partial product for the next stage.
4. carry-in input bit" cin" for the sum block.
5. carry out output bit "cout" from the sum block
6. output bits "m" and "q" that in fact, are just the input.

Preparing

• Draw a 1-bit x 1-bit cell entity,
• Draw a 1-bit x 1-bit cell architecture, 
• Draw the schematic diagram for the 2-bit x 2-bit multiplier, and the interconnections required for a 2-bit x 2-bit configuration. be sure to label, all signals with variable names and direction,
• (optional) write the VHDL code that corresponds to the schematic diagram in a structural form.

Lab Working

• Create a file adder.vhd
• Create two files mult1.vhd and mult2.vhd. the first file is the 1-bit multiplier cell that has the structural information on a gate level. the second file is the entire 2-bit multiplier that requires multiple instances of the 1-bit multiplier connected with each other, and is the top level file in the hierarchy.
• Compile all the files, start from adder to 1-bit to 2-bit file. correct any error occurs during the compilation.
• Exhaustively tests all combinations of the 2-bit multiplier, from 0x0 to 3x3.
• If the test doesn't yield proper results, go back through it and your code files. recompile and retest.
• Annotate your waveforms with titles and descriptions of what is happening.

Part II : State Machines

Build a finite state machine that detects the overlapping patterns of "11001", and "1101" from a serial bit stream, When the state machine detects the pattern, it will set its output signal start to '1' for a clock cycle. For this, you will need to demonstration a state diagram, state reduction table, karnaugh maps and equations for implementation with D flip-flops. A final state diagram will be particularly useful for behavior implementation.

Preparing

• Draw a state diagram of your Moore or Mealy machine
• Derive the symbolic state table
• Reduce the state diagram
• Final assignment the state
• Final state table
• Find output function
• Schematic diagram
• Draw a reduced state diagram of your state machine
• draw out your Entity schematic of the detector

Lab Working

• Edit, Compile and simulate your VHDL code using the ModelSim-Altera and program your pattern detector on the DE1 SoC board based on 5CSEMA5F31C6 device.
• Test every transition of your state machine and show the state of your state machine in the simulation. Print off the waveform showing exhaustive testing and hand it in with your report.
• The waveforms must be annotated and have a title. The annotations must make it easier to determine that the waveforms show correct operation of your state machine.

Questions

1. For the 2-bit x 2-bit multiplier, describe the hierarchy of VHDL files in a tree format.
2. How can a hierarchy of VHDL files aid a digital designer? Is it a good idea to include a large design in one file?
3. Why is " exhaustive" testing not a practical method of test for every digital circuit? can you think of how a hierarchy can help you in testing?

Lab Submissions

• Lab submission has to include:
1. The preparing elements from Part I and Part II.
2. Your VHDL code from Part I and Part II
3. Your testbench files for Part I and Part II
4. Your annotated waveforms from Part I and Part II.
5. Answers to the lab questions.