-------------------------------------------------------------
-- A 4-1 Mux
-- Author       : ECED4260
-- Student ID   : ------
-- Date         : September xx, 2016
-- File Name    : Mux_4.vhd
-- Architecture : Structural
-- Description  : The select on the mux determines which
--                output appears at the output.
-- Acknowledgements:
-------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity Mux_4 is
    port (	
		Input  	: in std_logic_vector(3 downto 0);
		Sel	: in std_logic_vector(1 downto 0);
          	Output  : out std_logic
	);
end Mux_4;



architecture structural of Mux_4 is

component Mux_2
	port( 
		Input 	: in  std_logic_vector(1 downto 0);
		Sel	: in  std_logic;
		Output 	: out std_logic
	);
end component;

-- Declare the signals needed in the entity
signal internalMuxOut  : std_logic_vector(1 downto 0);

begin
	-- Create three Mux_2 components and connect them accordingly






end structural;