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-- A Xor 2 input gate  
-- Author	: ECED 4260
-- Student ID	: ------
-- Date	  	: September xx, 2020
-- File Name	: Xor_2.vhd
-- Architecture	: RTL
-- Description	: Two input xor gate 
--		  output appears at the output.
-- Acknowledgements:
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library IEEE;
use IEEE.std_logic_1164.all;

entity Xor_2 is
    port (	
		Input  	: in std_logic_vector(1 downto 0);
          	Output  : out std_logic
	);
end Xor_2;

architecture rtl of Xor_2 is

-- Declare the signals needed in the entity.
signal andSel  : std_logic_vector(1 downto 0);
signal Input_bar : std_logic_vector(1 downto 0);

begin

	Input_bar(0)  <= not Input(0);
	Input_bar(1)  <= not Input(1);
	andSel(0) <= Input_bar(0) and Input(1);
	andSel(1) <= Input_bar(1) and Input(0);
	Output    <= andSel(1) or andSel(0); 

end rtl;