Advanced MicroElectroMechanical Systems (A-MEMS) and Application Laboratory 





ECED 4260






 

    Assignment
    Post Date
    Submission Due Date (@11pm)	
  



	
	Assignment 1 and Reference Solution 1 
	
	
	Sept. 13 
		
	
	Sept. 27  
		





	
	Assignment 2 and Reference Solution 2  

         FSM VHDL code  and  Verilog code for Q4

	 FSM_Testbench  and  Verilog Testbench 
			
	
	Sept. 27 
		
	
	Oct. 14  
	



	

	
	Assignment 3 and Reference Solution 3 
	
	
	Oct. 14
		
	
	Oct. 28
		





	
	Assignment 4 and  Reference Solution 4 


			
	
	Nov. 1
		
	
	Nov. 12  
		





	
	Assignment 5 and  Reference Solution 5
	
	
	Nov. 20 
		
	
	Dec. 4  
		





     
  



    Tutorials
    Tutorial Dates
    Submission Due Date (@11pm)	
  




	
	
	Tutorial A: Quartus Prime _VHDL and  light.vhd 

	Tutorial A: Quartus Prime _Verilog and  light.v 

	  Tutorial A Sbmission Requirements 
			
	
	Sept. 12 
		
	
	Sept. 18 
		




	
	Intel Tutorial B: ModelSim Simulator_VHDL  

	Intel Tutorial B: ModelSim Simulator_Verilog  

	Tutorial B  Requirements 
			
	
	Sept. 19 
		
	
	Sept. 25
		




	Intel Tutorial C: VHDL Testbench  

	Intel Tutorial C: Verilog Testbench  

	Tutorial C  Requirements 
			
	
	Sept. 26
		
	
	Oct. 3
	
	


	Intel Tutorial D: Timing Analyzer - VHDL 

 	 Intel Tutorial D: Timing Analyzer - Verilog 

	Tutorial D  Requirements  

	Reference: 
Intel User Guide 
			
	
	Oct. 3

 Understanding Timing Analysis Video 
				
	
	Oct. 10
	



	Tutorial E: Debugging Hardware - VHDL 

 Tutorial E: Debugging Hardware - Verilog 
 Tutorial E  Requirements 

Reference: SignalTap_VHDL and SignalTap_Verilog 

 Pin Assignment File
			
	
	Oct. 10

Beat my  record!
				
	
	Oct. 16
		




     
  



    Labs
    Lab Dates
    Submission Due Date (@11pm)	
  




	
Lab1: Fundamentals of Digital Design 
 Download  Mux_2  and  Mux_4  here

Download  Mux_2.v ,  Mux_4.v  and Pattern Detector with errorshere

			
	
	
	Oct. 17

	PatternDetector Waveform Example 
				
	
	Oct. 23 
		







	Project Introduction/Preparation:
 A. GCD Calculator;
  B. Dice Game ; 
C. Beamformer;
  D. The S-Machine Instruction Set Architecture 		
	
	Oct. 24 (8:35-10:00) at B227

Quiz #1 (10-11:30) at C234
				
	
	---
		





	Lab2: Structual HDL and Testbench 
	
	Oct. 31
		
	
	Nov. 6th
		





     Project
    Work Sessions
    Submission Due Date (@11pm)	
  




	Project A/B/C/D

 Report Guidelines
			
	
	Nov. 7, 21, 28
		
	
	Dec. 8
		




	Project Presentation 
	
	
	Dec. 4, 6
		
	
	----
		




	
	
	
	Dec. 5 (Quiz #2, 1.5 hr)
		
	
	----
		







Software Installation:


Windows/Linux OS: Download Quartus Prime Lite Edition (v20) individual files:  

Quartus Prime (2.0 GB), ModelSim-Intel FPGA (1.3GB), Cyclone V Device file (1.3 GB)


Note: Quartus v18 from ECED2200 also works, see Tutorial A for adding Cyclone V device support


Mac: Install a dual boot of Windows then install Quartus Prime Lite.




Hardware References:


For USB-Blaster II Driver installation, see  Getting Started with Intel's DE-Series Boards  

For I/O pin assignment, see pp. 25-26 of the  DE1-SoC User Guide

For project ideas, check Intel FPGA Tutorials